1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device with a redundancy circuit in which power supply voltage dependence and temperature dependence of a critical resistance of a fuse are small.
2. Description of the Related Art
In a semiconductor memory device, the probability that a fault memory cell is contained increases as the memory capacity of the memory device increases. For this reason, in order to prevent the decrease of a production yield, a redundant memory cell area of a redundancy circuit is provided for the semiconductor memory device. When the fault memory cell is replaced by a redundant memory cell, the replacement by the redundant memory cell is carried out by setting an address of the fault memory cell to the fuse.
In the step that a semiconductor memory device is formed on a wafer, the operation confirmation of the memory device is carried out to detect any fault memory cell. A fuse is cut using a laser beam so that an address corresponding to the detected fault memory cell is set to the fuse. Then, the wafer is divided into chips, and each chip is incorporated into a package and is forwarded as the semiconductor memory device. In this way, a redundancy circuit is provided for spare memory cells to increase the production yield of the semiconductor memory device. A redundancy fuse of a fuse window of the redundancy circuit is set to the ON (not cut) or OFF (cut) state so that the address of the fault memory cell is specified.
Then, the semiconductor memory device is incorporated into an electronic appliance. When the electronic appliance is turned on and the fault memory cell is accessed, reading and writing operations are carried out to the redundant memory cell in place of the fault memory cell. In this case, conventionally, it is determined whether or not an address indicative of an address signal is coincident with the address set to the fuses, every time the address signal is supplied to the semiconductor memory device.
Recently, as the memory capacity increases, the number of redundancy circuits increases and the number of address signals increases, too. Therefore, it is necessary to use a lot of fuses for replacement by the redundancy memory cells in the redundant circuit. When the number of fuses increases, the signal lines connected with the fuses become long and a parasitic capacity of the signal line increases. For this reason, it takes a long time to read the ON/OFF state of the fuse.
Also, because a current flows to read the ON/OFF state of the fuse every time an address signal is supplied to the semiconductor memory device, the consumption current increases, too.
Therefore, a method is proposed in which the ON/OFF state of the fuse is determined in the initial step when a power supply is turned on, the determination result is latched and a redundancy circuit is accessed based on the latched determination result. Such a method is disclosed in U.S. Pat. No. 5,345,110 entitled "LOW-POWER FUSE DETECT AND LATCH CIRCUIT".
FIG. 1 shows a fuse determination circuit disclosed in the U.S. Pat. No. 5,345,110. The fuse determination circuit is composed of a redundant fuse 10, an N-channel metal oxide semiconductor transistor 12, a P-channel MOS transistor 14, and inverters 16, 17 and 18. The one end of the fuse 10 is connected with the ground potential and the source of the P-channel transistor 14 is connected with a power supply voltage Vcc. The N-channel transistor 12 and the P-channel transistor 14 and the inverter 16 form the fuse determining section. Two inverters 17 and 18 are connected in a reverse manner in parallel and forms the latch section.
A pulse signal of a High level is externally supplied to an input terminal IN for a short time so as to read whether or not the fuse 10 is cut. The N-channel transistor 12 and the P-channel transistor 14 are turned on during the High level period of the pulse signal on the input terminal IN. When the fuse is completely cut, a determination node B is set to the High level so that an output terminal OUT is set to a Low level via the inverter 17. The Low level output is fed back to the determination node B via the inverter 18 and the data is latched.
On the other hand, when the fuse is not completely cut, the current flows through the N-channel transistor 12 and the P-channel transistor 14 so that the determination node B is set to the Low level. The output terminal OUT is set to the High level via the inverter 17. The High level output is fed back to the determination node B via the inverter 18 and the data is latched.
In this reference, the gate width of the transistor is adjusted in such a manner that the ON resistance of the N-channel transistor 12 is small, compared with the ON resistance of the P-channel transistor 14. Therefore, even if the transistors 12 and 14 are turned on at the same time, the voltage of the determination node B can be set to the Low level. Thus, the ON/OFF state of the fuse can be determined based on the signal from output terminal OUT.
The cutting of the fuse is generally carried out using a laser beam. In this case, there is a case that the fuse is not completely cut. This state is referred to as a partially-cut state in the specification. In case of such a "partially-cut" state, the voltage of the determination node B is determined by the ratio of the ON resistance of the P-channel transistor 14 and the resistance of the fuse 10 in the partially-cut state. When the voltage of the determination node B exceeds the threshold of the inverter 17, the output terminal OUT is set to the Low level. Also, when the voltage of the determination node B does not exceed the threshold of the inverter 17, the output terminal OUT is set to the High level. In this way, the state of ON/OFF of the fuse is determined based on whether the voltage of the determination node B exceeds the threshold of the inverter 17, even when the fuse is in the partially-cut state. It should be noted that the resistance value of the fuse as a reference when whether the fuse is in the ON state or the OFF state is determined is referred to as a critical resistance.
The conventional fuse determination circuit shown in FIG. 1 has the following problem. That is, because the voltage Vgs between the gate and the source in the P-channel transistor 14 changes largely depending upon the power supply voltage Vcc, the ON resistance of the P-channel transistor 14 changes when the power supply voltage Vcc changes. As a result, the ratio of the ON resistance and the resistance of the fuse changes so that the power supply voltage dependence of the critical resistance of the fuse becomes large. Also, the critical resistance of the fuse depends on the temperature. Therefore, when the fuse is not cut completely so that the resistance of the fuse is a value near the critical resistance, there would be a case where the ON state and the OFF state of the fuse is determined oppositely depending on the power supply voltage and the temperature.
Usually, the semiconductor memory device is applied with a predetermined power supply voltage at the room temperature and the voltage of the output terminal OUT is confirmed. If the output terminal OUT is in the Low level, the laser beam is irradiated once again to cut the fuse. However, if the output terminal OUT is in the High level, it is regarded that the fuse is completely cut, even if the fuse is in the partially-cut state. Thus, the test is ended.
The semiconductor memory devices with the fuse in the partially-cut state could be further removed if the power supply voltage and the temperature are changed and the test is repeated. However, an enormous time is taken for the test and the production cost of the semiconductor memory device increases.
Also, if usage ranges of the power supply voltage and the temperature are limited, the probability of the erroneous determination becomes low. However, the semiconductor memory device is limited in a practical use and can be used only for a special electronic appliance. Therefore, the possibility that the defective product could not be excluded through the test of the memory device increases.
As described above, depending on the power supply voltage, the semiconductor memory device which is determined as the OFF state through the test is possibly determined as the ON state. As a result, a data could not be correctly read from and written in the memory device.
Moreover, in the conventional fuse determination circuit, the gate of the P-channel transistor 14 is driven with a logic level of the High level or the Low level. Therefore, it is not possible to decrease a DC current which flows through the fuse 10 at the time of the level determination and the consumption power of the fuse determining section can not be adjusted.
If the semiconductor memory device apparatus has an internal circuit for stabilizing the power supply voltage, the dependence on the external power supply voltage can be decreased. In this case, however, elements increase to form the stabilizing circuit. Also, two wiring lines for the external power supply and the internal power supply must be arranged. Therefore, the layout area of the semiconductor memory device becomes large. Moreover, even if the power supply voltage dependence can be reduced, the temperature dependence cannot be compensated.
In the conventional fuse determination circuit, because the ON resistance of the P-channel transistor 14 and the resistance of fuse 10 are compared, the relation of (the size of the P-channel transistor 14)&lt;(the size of the N-channel transistor 12) is necessary to be satisfied. Hundreds of fuse determination circuits are formed on the chip. Therefore, the layout area becomes large when the size of the N-channel transistor 12 becomes large.
Also, during the High level period of the pulse signal on the input terminal IN, the determination node B is driven by the P-channel transistor 14 and fuse 10. However, there is a problem that the critical resistance of the fuse changes depending upon the previous latch state because of competition with the inverter 18.